This application relates generally to binary voltage-differential sensing circuits, and particularly to differential amplifier circuits for sensing small differences in potential between two circuit points or nodes, and producing an amplified binary output set by the sense (plus or minus) of the potential difference. Such differential amplifer circuits are particularly useful in sense/refresh amplifier circuits for semiconductor random-access memory (RAM) circuits.
In accordance with one typical type of prior known RAM circuit, such as described in my prior U.S. Pat. No. 3,838,404, herein incorporated by reference, a binary charge (0 volts or a cell charge V.sub.M) on a semiconductor memory cell capacitor is sensed by racing balanced load capacitances up or down from a preset equal state to unbalance a flip-flop circuit of the sense/refresh amplifier and set a binary output related to the sensed charge on the cell capacitor. One problem with this technique is that it requires very closely balanced values of load capacitance, which is difficult to achieve in manufacture and the final values of which are hard to predict prior to manufacture of each chip.
This requirement of balanced load capacitances on either side of the sense/refresh amplifier makes it particularly difficult to fabricate a "single-ended" or one-sided semiconductor memory, with a large array of memory cells located together in a single area of the chip; that is, all on one side of the sense/refresh amplifier section. As described in my prior patent, with balanced load capacitances to sense memory cell voltages, it is most convenient to divide the memory cells into two equal banks, one on either side of the sense/refresh amplifier, for input/output to and from the amplifier on opposite sides. With this arrangement the values of distributed load capacitance on each side tend to be equalized in the manufacturing process.